Some modern transceiver circuitry used in, for example, mobile communication devices, requires clock signals of various frequencies from frequency division circuitry. For example, in the receiver portion of a transceiver, a local oscillator (LO) frequency is typically a division of a given reference frequency. A programmable frequency divider is often included in phase locked loop (PLL) circuits to generate a desired LO frequency. In the transmitter portion of the transceiver, a programmable frequency divider is typically included in transmission loops to help generate a necessary radio frequency (RF) or intermediate frequency (IF).
Referring to FIG. 1, a basic block diagram of a frequency divider 100 is provided. A clock-in signal 102 is input into the frequency divider 100. The DIV input 104 represents a desired division ratio. DIV is sometimes an array or vector of N+1 bits for indicating the division ratio. For example, to represent a division ratio ranging from 1-8, an array of 3 or more bits could be used. The load signal 106 is a signal used to load a state in the frequency divider 100 such that the proper division ratio of the clock-in signal 102 will be performed. The clock-out signal 108 is the resultant divided down output signal.
FIG. 2 is a block diagram of a prior art frequency divider 200. The core of this frequency divider is a counter 202, which counts according to the division ratio set by the DIV input 204. The counter 202 counts the clock cycles of the clock input 206 to enable generation of a count waveform 208 that has a frequency equal to the frequency of the clock input 206 divided by the division ratio represented by DIV 204. The additional logic 210 handles both odd and even division ratio inputs. Negative edges of the clock input 206 can be used in the processing of odd division ratios and thereby provide a balanced 50/50 duty cycle clock output 212. If the division ratio, DIV 204 is “large”, for example between 4 and 1024, then the increased complexity of the counter block 202 creates a substantial design limitation on the allowable maximum clock-in frequency 206. This is due to the logic in the counter 202 becoming more complex as the DIV number becomes larger thereby having a consequence of creating a critical delay time for the timing of the counter circuitry 202 to creation of the clock-out signal 212 with respect to the clock-in signal 206. It has been shown through computer analysis that when using CMOS040 technology (CMOS-40 nm technology) the maximum frequency for the clock-in signal 206 is about 910 MHz when N equals 3 (i.e., N+1=4 bits) and the division ratio input 204 has a value ranging from 1 to 16. Creating high frequency division circuits using prior art counter-style frequency divider cannot physically operate at frequencies over about 910 MHz and operate with a division ratio greater than 16 using CMOS-40 nm technology.
Thus, a problem that needs to be addressed is to resolve how to minimize the critical timing delay at a frequency divider circuit when the DIV or division ratio 204 is a large number (i.e., represented as a division ratio between 4 and 1024). For example, if a clock-in signal 206 is 910 MHz (which is less than one GHz) and N=3, then this prior art frequency divider will work properly. But, for example, if N=5 or more then the frequency division of this prior art frequency divider 200 becomes impossible because there is not enough set-up time for the flip-flop devices within the counter block 202 to operate correctly. Therefore, what is needed is a frequency division design that allows for programmable frequency division of a clock input such that whatever number is selected as the division ratio, substantially the same performance of the division aspect of the frequency division circuitry is provided regardless of how complex or large the division circuit becomes. Further, it would be advantageous to be able to provide a frequency divider device wherein the DIV (the division ratio) can be increased without limiting the maximum clock-in frequency.
Additionally, it would be advantageous to provide such a high speed clock frequency divider architecture that can provide the 50% duty cycle clock-output regardless of whether the division ratio is an odd or even positive integer.